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| copyright ? cirrus logic, inc. 2013 (all rights reserved) cirrus logic, inc. http://www.cirrus.com cs1615 cs1616 single stage dimmable offline ac/dc controller for led lamps features ? best-in-class dimmer compatibility - leading-edge (triac) dimmers - trailing-edge dimmers - digital dimmers (dimmers with an integrated power supply) ? flicker-free dimming ? 0% to 100% smooth dimming ? primary-side regulation (psr) ? active power factor correction (pfc) - >0.9 power factor ? constant-cu rrent output - flyback - buck-boost ? tight led current regulation: better than 5% ? low thd: less than 20% ? up to 90% efficiency ? fast startup ? iec61000-3-2 compliant ? meets nema ssl 6 dimming standard - closely matches incandescent s-curve ? protection features - output open circuit - output short circuit - external overtemperature using ntc overview the cs1615 and cs1616 are high-performance single stage dimmable offline ac/dc controllers. the cs1615/16 is a cost-effective solution that provides unmatched single- and multi-lamp dimmer-compatibility performance for dimmable led applications. the cs1615 is designed for 120vac line voltage applications, and the cs1616 is designed for 230vac line voltage applications. across a broad range of dimmers, the cs1615/16 provides smooth flicker free dimming, and consistently dims to nearly zero light output, which closely matches the dimming performance of incandescent light bulbs. cirrus logic?s patent pending approach to dimmer compatibility provides full functionality on a wide range of dimmers, including leading-edge, trailing-edge, and digital dimmers. applications ? retro-fit led lamps ? external led drivers ? led luminaries ? commercial lighting ordering information see page 14 . ac mains br1 br1 br1 br1 cs1615/16 fbaux gnd iac r3 t1 c7 gd led+ vdd source eotp ntc 5 16 13 10 14 r s d2 led- d4 r2 d1 q1 z1 fbsense d3 r6 c6 q3 r sense 11 2 12 sgnd 4 ctrl1 ctrl2 r ctrl1 r ctrl2 89 c1 c2 c5 c4 c3 d5 r7 c8 r8 v rect l1 v aux q2 v aux r4 r5 r1 jun?13 ds961f1
cs1615/16 2 ds961f1 1. introduction figure 1. cs1615/16 block diagram a typical schematic using the cs1615/16 ic is shown on the previous page. startup current is provided from a patent-pending, external, high- voltage source-follower network. in addition to providing startup current, this unique topology is in tegral in providing compatibility with digital dimmers by ensuring v dd power is always available to the ic. during normal operation, an auxiliary winding on the flyback transformer or buck-boost inductor back-biases the source-follower circuit and prov ides steady-state operating current to the ic to improve system efficiency. rectified input voltage v rect is sensed as a current into pin iac and is used to control t he adaptive dimmer-compatibility algorithm and to extract the phase of the input voltage for output dimming control. the source pin is used to provide a control signal for the high-voltage source-follower circuit during leading- edge mode and trailing-edge mode; it also provides the current during startup. the digital dual-mode controller is implemented with peak- current mode primary-side regulati on, which eliminates the need for additional components to provide feedback from the secondary and reduces system co st and complexity. voltage across a user-selected resistor is sensed through pin fbsense to control the peak current of the primary-side inductor. leading- edge and trailing-edge blanking on pin fbsen se prevents false triggering. the required target led current and average flyback transformer and buck-boost inductor input current are set by attaching resistors r ctrl1 and r ctrl2 on pins ctrl1 and ctrl2, respectively. the cont roller ensures half line-cycle averaged constant output current. pin fbaux is used for zero-c urrent detection to ensure quasi-resonant switching of the single stage output. when an external negative temperature coefficient (ntc) thermistor is connected to pin eotp, the cs1615/16 monitors the system temperature, allowing the controlle r to reduce the output current of the system. if the temperatur e reaches a designated high set point, the ic is shut down and stops switching. 2 iac source 5 sgnd 15k adc i ref 11 fbsense + - dac + - peak control 12 gnd olp + - ocp blank 3 clamp v ocp (th) v olp (th ) v pk_max (th) i clamp + - v source(th) mux 9 + - i connect v connect(th) 10 ctrl2 8 ctrl1 eotp fbaux 16 + - zero -current detect + - output overvoltage v zcd(th) v ovp(th ) t vaux 14 vdd + - v dd(on) v dd(off) voltage regulator v z por 13 gd vdd vdd vdd 4 + - v fs ta rt(th ) 3 cs1615/16 ds961f1 3 2. pin description figure 2. cs1615/16 pin assignments 16 -lead soic and tssop 16 zero-current detect fbaux 15 no connect nc 14 ic supply voltage vdd 13 gd gate drive 10 eotp external overtemperature protection 11 fbsense flyback current sense 12 gnd ground 9 led load current ctrl2 no connect nc 1 2 iac rectifier voltage sense 3 voltage clamp current source clamp 4 sgnd source ground 5 source switch source 6 nc no connect 7 no connect nc 8 ctrl1 dimmer hold current pin name pin # i/o description nc 1in no connect ? leave pin unconnected. iac 2in rectifier voltage sense ? a current proportional to t he rectified line voltage is fed into this pin. the current is measured with an a/d converter. clamp 3out voltage clamp current source ? connect to a voltage clamp circuit on the source-switched dimmer-compatibility circuit. sgnd 4pwr source ground ? common reference current return for the source pin. source 5in source switch ? connected to the source of the source-switched external high-volt- age fet. nc 6in no connect ? connect this pin to vdd using a 47k ? pull-up resistor. nc 7in no connect ? connect this pin to vdd using a 47k ?? pull-up resistor. ctrl1 8in dimmer hold current ? connect a resistor to this pi n to set the minimum input cur- rent being pulled by the flyback/buck-boost stage. ctrl2 9in led load current ? connect a resistor to this pin to set the led current. eotp 10 in external overtemperature protection ? connect an external ntc thermistor to this pin, allowing the internal a/d converter to sample the change to ntc resistance. fbsense 11 in feedback current sense ? the current flowing in the power fet is sensed across a resistor. the resulting voltage is applied to this pin and digitized for use by the compu- tational logic to determine the fet's duty cycle. gnd 12 pwr ground ? common reference. current return for both the input signal portion of the ic and the gate driver. gd 13 out gate drive ? gate drive for the power fet. vdd 14 pwr ic supply voltage ? connect a storage capacitor to this pin to serve as a reservoir for operating current for the device, includin g the gate drive current to the power tran- sistor. nc 15 - no connect ? leave pin unconnected. fbaux 16 in zero-current detect ? connect to the flyback/buck-boost inductor auxiliary winding for demagnetization current zero-crossing detection. cs1615/16 4 ds961f1 3. characteristics and specifications 3.1 electrical characteristics typical characteristics conditions: ?t a =25c, v dd =12v, gnd=0v ? all voltages are measured with respect to gnd. ? unless otherwise specified, all currents are positive when flowing into the ic. minimum/maximum characteristics conditions: ?t j = -40c to +125 c, v dd = 11v to 17v, gnd = 0 v parameter condition symbol min typ max unit vdd supply voltage operating range after turn-on v dd 11 - 17 v turn-on threshold voltage v dd increasing v st(th) -8.5-v turn-off threshold voltage (uvlo) v dd decreasing v stp(th) -7.5-v zener voltage (note 1) i dd =20ma v z 18.5 - 19.8 v vdd supply current startup supply current v dd cs1615/16 6 ds961f1 3.2 thermal resistance 3.3 absolute maximum ratings characteristics conditions: all voltages are measured with respect to gnd. note: 8. long-term operation at the maximum junction temperature wi ll result in reduced product life. derate internal power dissi pation at the rate of 50 mw /c for variation over temperature. warning: operation at or beyond these limits may re sult in permanent damage to the device. normal operation is not guaranteed at these extremes. symbol parameter soic tssop unit ? ja junction-to-ambient thermal impedance 2 layer pcb 4 layer pcb 119 105 138 103 c/w c/w ? jc junction-to-case thermal impedance 2 layer pcb 4 layer pcb 50 44 44 28 c/w c/w pin symbol parameter value unit 14 v dd ic supply voltage 18.5 v 2,8,9, 10,11,16 analog input maximum voltage -0.5 to (v dd +0.5) v 2,8,9, 10,11,16 analog input maximum current 5 ma 13 v gd gate drive output voltage -0.3 to (v dd +0.3) v 13 i gd gate drive output current -1.0 / +0.5 a 5i source current into pin 1.1 a 3i clamp clamp output current 15 ma -p d total power dissipation 400 mw -t j junction temperature operating range (note 8) -40 to +125 c -t stg storage temperature range -65 to +150 c all pins esd electrostatic discharge capability human body model charged device model 2000 500 v v cs1615/16 ds961f1 7 4. typical performance plots figure 3. uvlo characteristics figure 4. supply current vs. voltage figure 5. turn on/off threshold voltage vs. temperature figure 6. zener voltage vs. temperature figure 7. gate drive resistance vs. temperature figure 8. reference current (i ref ) drift vs. temperature 0 1 2 3 -50 0 50 100 150 uvlo hysteresis temperature (oc) -2 0 2 4 6 8 02468101214161820 i dd (ma) v dd (v) falling edge rising edge 7 8 9 10 -50 0 50 100 150 vdd (v) temperature (oc) turn off turn on 18 18.5 19 19.5 20 125 105 85 55 25 5 -20 -45 v z (v) temperature (oc) 0 5 10 15 20 25 30 35 resistance ( ? ) temperature (oc) sink source -43 25 125 -2.25 -1.75 -1.25 -0.75 -0.25 0.25 125 105 85 55 25 5 -20 -45 drift (%) temperature ( c) cs1615/16 8 ds961f1 5. general description 5.1 overview the cs1615 and cs1616 are high-performance single stage dimmable offline ac/dc controllers. the cs1615/16 is a cost- effective solution that provides unmatched single- and multi-lamp dimmer-compatibility performance for dimmable led applications. the cs1615 is designed for 120vac line voltage applications, and the cs1616 is designed for 230vac line voltage applications. across a broad range of dimmers, the cs1615/16 provides smooth flicker free dimming, and co nsistently dims to nearly zero light output, which closely ma tches the dimming performance of incandescent light bulbs. cirrus logic?s patent pending approach to dimmer compatibility provides full functionality on a wide range of dimmers, including leading- edge, trailing-edge, and digital dimmers. 5.2 ic startup a high-voltage source-follower circ uit is used to deliver startup current to the ic. during st eady-state operation, an auxiliary winding on the transformer/inductor biases this circuit to an off state to improve syste m efficiency, and all ic supply current is provided from the auxiliary winding. the patent-pending technology of the high-voltage s ource-follower circuit enables system compatibility with digita l dimmers (dimmers containing an internal power supply) by providing a continuous path for the dimmer?s power supply to recharge during its off state. during steady-state operation, high-voltage fet q1 in this circuit is source-controlled by a variable internal current source on the source pin to create the dimmer-compatibility circuit. a schottky diode with a forward voltage of less than 0.6v is recommended for diode d1. schottky diode d1 will limit inrush current through the internal dio de, preventing damage to the ic. during initial power-up, the ic ex ecutes a fast startup algorithm, which drives the converter wit h peak currents that are above normal to charge the output capacitor. once the output capacitor reaches a defined voltage, the ic drives the converter with nominal peak currents until normal operation is achieved. 5.3 ic operation 5.3.1 dimmer detection the cs1615/16 dimmer switch detection algorithm determines if a non-dimming switch, a leading-edge dimmer switch, or a trailing-edge dimmer switch controls the solid-state lighting (ssl) system. for each type of switch, t he ic uses a different operating mode: for a non-dimming switch, no-dimmer mode is used; for a leading-edge dimmer switch, leading-edge mode is used; for a trailing-edge dimmer switch, trailing-edge mode is used. as a result, the overall performance is optimized in terms of power losses, efficiency, power factor , thd, and dimmer compatibility. when the ic completes uvlo, it executes in leading-edge mode until the dimmer switch detec tion algorithm determines the appropriate operating mode for the ic. the dimmer switch detection algorithm uses the input line voltage slope and dimmer phase angle to determine the operating mode that matches the type of dimmer switch in the syst em. from there on, it periodically learns the dimmer type and can change the operating mode if the type of dimmer switch changes. 5.3.1.1 no-dimmer mode if the cs1615/16 determines that the line is not phase cut by a dimmer switch, the ic operates the flyback/ buck-boost in pfc mode to achieve a power factor greater than 0.9 while regulating the load current to a level set by resistor r ctrl2 . in addition, a no-dimmer mode algorithm is ap plied to the source-controlled dimmer-compatibility circuit fo r optimal performance, including less than 20% of thd and highest possible overall efficiency. 5.3.1.2 leading-edge mode if the cs1615/16 determines that the line is phase cut by a leading-edge dimmer switch, the ic operates the flyback/buck- boost in dimmer mode and the ic sets the dimmer firing current as well as the attach current using a source-controlled dimmer- compatibility circuit for stab le triac dimmer operation. 5.3.1.3 trailing-edge mode if the cs1615/16 determines that the line is phase cut by a trailing-edge dimmer switch, the ic operates the flyback/buck- boost in dimmer mode. the ic charges the capacitor in the figure 9. no-dimmer mode waveform figure 10. leading-edge mode phase-cut waveform cs1615/16 ds961f1 9 dimmer switch on the falling edge of the input voltage using a source-controlled dimmer-compatibility circuit. 5.3.2 switch overpower protection to prevent excessive power dissipation on the source-switched fet q1, the cs1615/16 monitors voltage across fet q1 and current flow through fet q1 to calculate average power dissipation. if the calculated power exceeds the overpower protection threshold a fault condition occurs. the ic output is disabled and the controller attempts to restart after approximately thirty seconds. 5.4 voltage clamp circuit to keep trailing-edge dimmer switches conducting and from misfiring, the dimmer switch internal capacitor has to be charged quickly around the trailing edge of the phase-cut waveform. in addition to the dimmer compatible circuit, an optional clamp circuit provides a high-current sinking path for delivering the required amount of charge onto the dimmer switch capacitor in a short amount of time. the cs1615/16 provides active clamp circuitry on the clamp pin, as shown in figure 12. 5.4.1 clamp overpower protection the cs1615/16 clamp overpower protection (cop) control logic averages the turn-on time of the cl amp circuit. if the output of the averaging logic exceeds 10%, a cop event is actuated. the clamp circuit is disabled as well as the flyback/buck-boost controller and the dimmer-compatibility circuit. the cop fault state is not cleared until the powe r to the ic is recycled. 5.5 dimmer angle extraction and the dim mapping algorithm when operating with a dimmer, the dimming signal is extracted in the time domain and is proportional to the conduction angle of the dimmer. a control variable is passed to the quasi-resonant flyback/buck-boost controller to achieve a wide range of output currents. 5.6 dual-mode flyback/buck-boost the cs1615/16 is configurable for isolated or non-isolated topologies using a flyback transformer or buck-boost inductor, respectively. the cs1615/16 controls the dual-mode flyback/buck-boost to satisfy the dimmer hold current requirement in dimmer mode and provide power factor correction in no-dimmer mode. the dual-mode ensures a minimum average input current greater than the required dimmer hold current when behind a dimmer and shapes the line current when not behind a dimmer to provide power factor correction. it also ensures half line-cycle aver aged constant output current. figure 13 illustrates the dual-mode flyback topology. the cs1615/16 regulates output curr ent using primary-side control, which eliminates the need for opto-coupler feedback. the control loop operates in peak current control mode. demagnetization time of the transformer is sensed by the fbaux pin using an auxiliary winding and is used as an input to the control loop. figure 11. trailing-edge mode phase-cut waveform clamp r clam p i clam p v rect s1 cs1615 /16 vdd q t1 r4 d3 r6 c6 r5 q3 r sense 3 13 gd 2 iac figure 12. clamp pin model r ctrl2 ctrl2 fbaux gnd gd 9 12 cs1615/16 16 13 t1 d3 r6 c6 q3 r sense v rect fbsense 11 c7 led+ led- r7 c8 r8 v aux d5 d4 figure 13. flyback model cs1615/16 10 ds961f1 figure 14 illustrates the dual-mode buck-boost topology. the cs1615/16 regulates the output current by controlling the peak current to ensure that the targ et output charge is achieved every half line-cycle. demagneti zation time of the inductor is sensed by the fbaux pin using an auxiliary winding and is used as an input to the control loop. 5.6.1 primary-side current control all input current shaping and output power transfer is attained using a peak current control algor ithm. demagnetization time of the primary inductor is sensed by the fbaux pin using an auxiliary winding and is used as an input to the control algorithm. the values obtained from resistors r ctrl1 and r ctrl2 are the other inputs to the control algor ithm that help shape the input current and control the led current, respectively. 5.6.2 output current regulation the cs1615/16 regulates output current by controlling the charge transferred over a half line-cycle. the full-scale output current target is set using resistor r ctrl2 , which is connected on pin ctrl2. this pin is sampled periodically by an adc. the value of this resistor can be determined using equation 1. where, n = turns ratio i out = current through led at maximum output r sense = resistor attached to pin fbsense when designing a buck-boost topology the turns ratio n is set to one. the cs1615/16 uses the value obtained from the resistor along with the phase-cut and line-cycle period information to determine the corresponding target full-scale output charge. the ic controls the inductor switching frequency and peak current to ensure that the target output charge is ac hieved every half line-cycle, thus regulating the output current. 5.6.3 input current shaping the cs1615/16 shapes the input current by controlling the peak primary current and the flyback/ buck-boost switching frequency. it shapes the currents differently when behind a dimmer compared to when not behind a dimmer. 5.6.3.1 operation behind a dimmer operating behind a dimmer, the cs1615/16 controls the switching frequency to ensure that the average input current is greater than the dimmer hold current requirement. the dimmer hold current level is sensed using resistor r ctrl1 on pin ctrl1, which is sampled periodically by an adc. the value of this resistor can be determined using the formula shown in equation 2. where, i in(cc) = constant input current used when designing circuit r sense = resistor attached to pin fbsense 5.6.3.2 operation in no-dimmer mode operating in no-dimmer mode , the cs1615/16 controls the switching frequency to ensure that the average input current follows the line voltage to provide power factor correction. in no- dimmer mode the controller is designed to operate in quasi- resonant mode to improve efficiency. 5.6.4 max primary-side switching current maximum primary-side switching current i pk(max) is set using resistor r sense connected to pin f bsense of the cs1615/16. the maximum primary-side switch ing current can be calculated using equation 3. 5.6.5 auxiliary winding configuration the auxiliary winding is used for zero-current detection (zcd), overvoltage protection (ovp), fa st startup, and the steady-state power supply. the voltage on the auxiliary winding is sensed through pin fbaux of the cs1615/16 for zero-current detection, overvoltage protection, and fast startup. the auxiliary winding is also used to provide the steady-state power supply to the cs1615/16. 5.6.6 output open circuit protection output open circuit protection and output overvoltage protection (ovp) are implemented by monitoring the output voltage through the transformer auxiliary winding. if the voltage on the fbaux pin exceeds a threshold v ovp(th) of 1.25v, a fault condition occurs. the ic output is disabled and the controller attempts to restart after approximately one second. r ctrl2 ctrl2 fbaux gnd gd 9 12 cs1615/16 16 13 q3 r sense v rect fbsense 11 led+ led- l2 r7 r8 d4 d5 c8 v aux c7 figure 14. buck-boost model r ctrl2 1.4v n 4m ? ? ? 1.25 511 ? r sense i out ? ? ----------------------------------------------------------------------- - = [eq.1] r ctrl1 1.4v 4m ? ? 511 i in cc ?? r sense ? ? ----------------------------------------------------------- - = [eq.2] i pk max ?? 1.4 r sense ------------------ - = [eq.3] cs1615/16 ds961f1 11 5.6.7 overcurrent protection overcurrent protection (ocp) is implemented by monitoring the voltage across the sense resistor . if this voltage exceeds a threshold v ocp(th) of 1.69v, a fault condition occurs. the ic output is disabled and the controller attempts to restart after approximately one second. 5.6.8 open loop protection open loop protection (olp) and sense resistor short protection are implemented by monitoring the voltage across the resistor. if the voltage on pin fbsense do es not reach the protection threshold v olp(th) of 200mv, the ic outpu t is disabled, and the controller attempts to restart after approximately one second. 5.7 overtemperatu re protection the cs1615/16 incorporates internal overtemperature protection (iotp) and the ability to connect an external overtemperature sense circuit for ic protection. typically, an ntc thermistor is used. 5.7.1 internal overtemperature protection internal overtemperature protecti on (iotp) is activated, and switching is disabled when the die temperature of the devices exceeds 135c. there is a hysteresis of about 14c before resuming normal operation. 5.7.2 external overtemperature protection the external overtemperature pr otection (eotp) pin is used to implement overtemperature protec tion. a negative temperature coefficient (ntc) thermistor resist ive network is connected to pin eotp, usually in the form of a series combination of a resistor r s and a thermistor r ntc (see figure 15). the cs1615/16 cyclically samples the resistance connected to pin eotp. the total resistance on the eotp pin gives an indication of the temperature and is used in a digital feedback loop to adjust current i connect into the ntc and series resistor r s to maintain a constant reference voltage v connect(th) of 1.25v. current i connect is generated from a controlled current source with a full-scale current of 80 ? a. when the loop is in equilibrium, the voltage on the eotp pin fluctuates around reference voltage v connect(th) . a resistance adc is used to generate current i connect . the adc output is filtered to suppress noise and compared against a reference that corresponds to 125c. a second low-pass filter with a time constant of two seconds filters the adc output and is used to scale down the internal dim level of the system (and hence led current i led ) if the temperature exceeds 95 c. the large time const ant for this filt er ensures that the dim scaling does not happen spontaneously and is not noticeable (suppress spurious glitches). the eotp tracking circuit is designed to function accurately with external capacitance up to 470pf. the tracking range of this resistance adc is approximately 15.5k ? to 4m ? . the series resistor r s is used to adjust the resistance of the ntc to fall within the adc tracking range, allowing the entire dynamic range of the adc to be well used. the cs1615/16 recognizes a resistance (r s +r ntc ) equal to 20.3k ??? which corresponds to a temperature of 95c, as the beginning of an overtemperature dimming event and starts reducing the power dissipation. th e output current is scaled until the series resistance (r s +r ntc ) value reaches 16.6k ? (125c). beyond this temperature, the ic shuts down until the resistance (r s +r ntc ) rises above 19.23k ? . this is not a latched protection state, and the adc keeps tracking the temperature in this state in order to clear the fault stat e once the temperature drops below 110c. when exiting reset, the chip ente rs startup and the adc quickly (<5ms) tracks the external temperat ure to check if it is below the 110c reference code before the c ontroller is powered up. if this check fails, the chip will wait until this condition becomes true before initializing t he rest of the system. for example, a 14 k ? (1% tolerance) series resistor is required to allow measurements of up to 130c to be within the eotp tracking range when a 100k ? ntc with a beta of 4275. if the temperature exceeds 95c, thermistor r ntc is approximately 6.3k ? and series resistor r s is 14k ? , so the eotp pin has a total resistance of 20.3k ? . the eotp pin initiates protective dimming action by reducing the power diss ipation. at 125c the thermistor r ntc has 2.6k ? plus a series resistor r s equal to 14k ? present a resistance of 16.6k ? at the eotp pin reaching the point where a thermal shutdown fault intervenes. the cs1615/16 will continue to monitor pin eotp and once the series resistor r s plus the thermistor r ntc rises above 19.23k ? the device will resume power conversion (see figure 16). if the external overtemperature protection feature is not required, connect the eotp pin to gnd using a 50k ? -to-500k ? resistor to disable the eotp feature. cs1615/16 + - i connect v connect (th) comp _out eotp control eotp r s c ntc ntc v dd 10 (optional ) figure 15. eotp functional diagram temperature ( c ) cu rrent (i led , nom.) 125 95 50% 100% 0 25 figure 16. eotp temperature vs. impedance cs1615/16 12 ds961f1 6. package drawing 1. controlling dimensions are in millimeters. 2. dimensioning and tolerances per asme y14.5m. 3. this drawing conforms to je dec outline mo-153, variation ab. 4. recommended reflow profile is per jedec/ipc j-std-020. mm inch dimension min nom max min nom max a - - - - 1.20 - - - - 0.047 a1 0.05 - - 0.15 0.002 - - 0.006 b 0.19 - - 0.30 0.007 - - 0.012 c 0.09 - - 0.20 0.004 - - 0.008 d 4.90 5.00 5.10 0.193 0.197 0.201 e 6.40 bsc 0.252 bsc e1 4.30 4.40 4.50 0.169 0.173 0.177 e 0.65 bsc 0.026 bsc l 0.45 0.60 0.75 0.018 0.024 0.030 0- -80- -8 aaa 0.10 0.004 bbb 0.10 0.004 ddd 0.20 0.008 4 & " 5 * / ( 1 - " / & 1 * / * / % * $ " 5 0 3 & & d f # % " " c $ " c c c $ # " % & 5 " * - " 5 0 1 7 * & 8 4 * % & 7 * & 8 & / % 7 * & 8 y e e e $ # " y 5 j q t % & 5 " * - " ( " 6 ( & 1 - " / & - t y b b b $ 16-pin tssop (173 mil body) cs1615/16 ds961f1 13 notes: 1. controlling dimensions are in millimeters. 2. dimensions and tolerances per asme y14.5m. 3. this drawing conforms to jedec outline ms-012, variation ac for standard 16 soicn narrow body. 4. recommended reflow profile is per jedec/ipc j-std-020. mm inch dimension min nom max min nom max a - - - - 1.75 - - - - 0.069 a1 0.10 - - 0.25 0.004 - - 0.010 b 0.31 - - 0.51 0.012 - - 0.020 c 0.10 - - 0.25 0.004 - - 0.010 d 9.90 bsc 0.390 bsc e 6.00 bsc 0.236 bsc e1 3.90 bsc 0.154 bsc e 1.27 bsc 0.050 bsc l 0.40 - - 1.27 0.016 - - 0.050 0- -80- -8 aaa 0.10 0.004 bbb 0.25 0.010 ddd 0.25 0.010 16-pin soicn (150 mil body) cs1615/16 14 ds961f1 7. ordering information 8. environmental, manufacturing , & handling information ordering number container ac line voltage temperature package cs1615-fsz bulk 120vac -40 c to +125 c 16-lead soicn, lead (pb) free CS1615-FSZR tape & reel cs1616-fsz bulk 230vac -40 c to +125 c 16-lead soicn, lead (pb) free cs1616-fszr tape & reel cs1615-fzz bulk 120vac -40 c to +125 c 16-lead tssop, lead (pb) free cs1615-fzzr tape & reel cs1616-fzz bulk 230vac -40 c to +125 c 16-lead tssop, lead (pb) free cs1616-fzzr tape & reel part number peak reflow temp msl rating a a.msl (moisture sensitivity level) as specified by ipc/jedec j-std-020. max floor life b b.stored at 30c, 60% relative humidity. cs1615-fsz 260 c 3 7 days cs1616-fsz 260 c 3 7 days cs1615-fzz 260 c 3 7 days cs1616-fzz 260 c 3 7 days cs1615/16 ds961f1 15 revision history revision date changes t1 jun 2012 initial release. pp1 jul 2012 corrected typographical errors. pp2 sep 2012 clarified context and corrected typographical errors. pp3 oct 2012 clarified context. pp4 jan 2013 buck-boost content added, and clarified context. pp5 apr 2013 context clarification. f1 jun 2013 final release cs1615/16 16 ds961f1 contacting cirrus logic support for all product questions and inquiries contact a cirrus log ic sales representative. to find the one nearest to you go to www.cirrus.com important notice cirrus logic, inc. and its subsidiaries ("cirrus") believe that the information contained in this document is accurate and reli able. however, the information is subject to change without notice and is provided "as is" without warranty of any kind (express or implied). customers are advised to ob tain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. all products are sold s ubject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pe rtaining to warranty, indemnification, and limitation of liabil ity. no responsibility is assumed by cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for in fringement of patents or other rights of third parties. this document is the property of cirrus and by furnishing this information, cirrus grants no license, express or impli ed under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. cirrus owns the copyrights associated with the inf ormation contained herein and gives consent for copies to be made of the information only for use within your organization with respect to cirrus integrated circui ts or other products of cirrus. this con- sent does not extend to other copying such as copying for gene ral distribution, advertising or promotional purposes, or for cre ating any work for resale. certain applications usin g semiconductor products may involv e potential risks of death, personal inj ury, or severe prop- erty or environmental damage ("critical applications"). cirr us products are not designed, authorized or warranted for use in products surgically implanted into the body, automotive safety or security devices, life suppor t products or other critical applications. inclusio n of cirrus products in such a pplications is understood to be fully at the customer's risk and cirrus disclaims and makes no warranty, express, statutory or implied, in cluding the implied warranties of merchant- ability and fitness for particular purpose, with regard to any cirrus product that is used in such a manner. if the customer or customer's customer uses or permits the use of cirrus pro ducts in critical applications, customer agrees, by such use, to fully indemnify cirrus, its offi cers, directors, emplo yees, distributors and other agents from any and all liability, in- cluding attorneys' fees and costs, that may result from or arise in connection with these uses. use of the formulas, equations, calculations, graphs, and/or other design guide information is at your sole discretion and does not guarantee any specific results or performance. the formulas, equations, graphs, and/or other design guide information are provided as a reference guide only and are intended to assist but not to be solely relied upon for design work, design calculations, or other purposes. cirrus logic makes no representations or warrant ies concerning the formulas, equa- tions, graphs, and/or other design guide information. cirrus logic, cirrus, the cirrus logic logo designs, exl core, and the exl core logo design are trademarks of cirrus logic, inc . all other brand and product names in this document may be trademarks or service marks of their respective owners. |
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